Example embodiments relate to semiconductor packages, fabrication methods thereof and/or semiconductor devices including one or more of the semiconductor packages, and more particularly, to chip stacked packages having a high bandwidth memory (HBM) structure and fabrication methods thereof, and/or semiconductor devices including one or more of the chip stacked packages.
As a demand for high performance characteristics for a stacked chip package implemented through a typical wire bonding technique increases, research has been conducted on a three-dimensional package employing a through silicon via (TSV) technique. In such three-dimensional packages, devices having various functions are stacked vertically such that expanded memory capacity, lower power consumption, higher transmission rate, and/or higher efficiency can be realized. One example of such three-dimensional packages is a HBM package in which a stacked layer of memory devices is packaged with, for example, a central processing unit (CPU) or a system on chip, by using a TSV interposer.